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general description the max11634Cmax11637 are serial 12-bit analog-to- digital converters (adcs) with an internal reference and true differential track/hold. these devices feature on-chip fifo, scan mode, internal clock mode, internal averag- ing, and autoshutdown?. the maximum sampling rate is 300ksps using an external clock. the max11636/ max11637 have 8 input channels and the max11634/ max11635 have 4 input channels. these four devices operate from either a +3v supply or a +5v supply, and contain a 10mhz spi?-/qspi?-/microwire?-compati- ble serial port. the max11634Cmax11637 are available in a 16-pin qsop package. all four devices are specified over the extended -40c to +85c temperature range. applications system supervision data-acquisition systems industrial control systems patient monitoring data logging instrumentation features analog multiplexer with true differential track/hold 8-/4-channel single-ended 4-/2-channel true differential unipolar or bipolar inputs single supply 2.7v to 3.6v (max11635/max11637) 4.75v to 5.25v (max11634/max11636) external reference: 1v to v dd 16-entry first-in/first-out (fifo) scan mode, internal averaging, and internal clock accuracy: ? lsb inl, ? lsb dnl, no missing codes over temperature 10mhz 3-wire spi-/qspi-/microwire-compatible interface small 16-pin qsop package max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference ________________________________________________________________ maxim integrated products 1 19-5962; rev 1; 9/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information/selector guide part number of inputs su ppl y vo l t a g e ( v) temp range pin-package max11634 eee+t 4 single-ended/ 2 differential 4.75 to 5.25 -40c to +85c 16 qsop max11635 eee+t 4 single-ended/ 2 differential 2.7 to 3.6 -40c to +85c 16 qsop max11636 eee+t 8 single-ended/ 4 differential 4.75 to 5.25 -40c to +85c 16 qsop max11637 eee+t 8 single-ended/ 4 differential 2.7 to 3.6 -40c to +85c 16 qsop autoshutdown is a trademark of maxim integrated products, inc. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. evaluation kit available
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = 2.7v to 3.6v (max11635/max11637), v dd = 4.75v to 5.25v (max11634/max11636), f sample = 300khz, f sclk = 4.8mhz (external clock, 50% duty cycle), v ref = 2.5v (max11635/max11637), v ref = 4.096v (max11634/max11636) t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v cs , sclk, din, eoc , dout to gnd.........-0.3v to (v dd + 0.3v) ain0Cain5, ref-/ain6, cnvst/ ain7, ref+ to gnd.........................................-0.3v to (v dd + 0.3v) maximum current into any pin ............................................50ma continuous power dissipation (t a = +70c) qsop (single-layer board) (derate 8.3mw/c above +70c) .................................667mw operating temperature range ...........................-40c to +85c storage temperature range .............................-60c to +150c junction temperature ......................................................+150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units dc accuracy (note 3) resolution res 12 bits integral nonlinearity inl 1.0 lsb differential nonlinearity dnl no missing codes over temperature 1.0 lsb offset error 0.5 4.0 lsb gain error (note 4) 0.5 4.0 lsb offset error temperature coefficient 2 ppm/c fsr gain temperature coefficient 0.8 ppm/c channel-to-channel offset matching 0.1 lsb dynamic specifications (30khz sine-wave input, 300ksps, f sclk = 4.8mhz) max11635/max11637 71 signal-to-noise plus distortion sinad max11634/max11636 73 db max11635/max11637 -80 total harmonic distortion thd up to the 5th harmonic max11634/max11636 -88 dbc max11635/max11637 81 spurious-free dynamic range sfdr max11634/max11636 89 dbc intermodulation distortion imd f in1 = 29.9khz, f in2 = 30.2khz 76 dbc full-power bandwidth -3db point 1 mhz full-linear bandwidth s/(n + d) > 68db 100 khz package thermal characteristics (note 1) qsop junction-to-ambient thermal resistance ( ja )...............105c/w junction-to-case thermal resistance ( jc )......................37c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial .
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 2.7v to 3.6v (max11635/max11637), v dd = 4.75v to 5.25v (max11634/max11636), f sample = 300khz, f sclk = 4.8mhz (external clock, 50% duty cycle), v ref = 2.5v (max11635/max11637), v ref = 4.096v (max11634/max11636) t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units conversion rate external reference 0.8 power-up time t pu internal reference (note 5) 65 s acquisition time t acq 0.6 s internally clocked 3.5 conversion time t conv externally clocked (note 6) 2.7 s externally clocked conversion 0.1 4.8 external clock frequency f sclk data i/o 10 mhz aperture delay 30 ns aperture jitter < 50 ps analog input unipolar 0 v ref input voltage range bipolar (note 7) -v ref /2 +v ref /2 v input leakage current v in = v dd 0.01 1 a input capacitance during acquisition time (note 8) 24 pf internal reference max11634/max11636 4.024 4.096 4.168 ref output voltage max11635/max11637 2.48 2.50 2.52 v max11634/max11636 20 ref temperature coefficient tc ref max11635/max11637 30 ppm/c output resistance 6.5 k ref output noise 200 v rms ref power-supply rejection psrr -70 db external reference input ref- input voltage range v ref- 0 500 mv ref+ input voltage range v ref+ 1.0 v dd + 50mv v v ref+ = 2.5v (max11635/max11637), v ref+ = 4.096v (max11634/max11636), f sample = 300ksps 40 100 ref+ input current i ref+ v ref+ = 2.5v (max11635/max11637), v ref+ = 4.096v (max11634/max11636), f sample = 0 0.1 5 a digital inputs (sclk, din, cs , cnvst (note 9) max11634/max11636 0.8 input voltage low v il max11635/max11637 v dd x 0.3 v max11634/max11636 2.0 input voltage high v ih max11635/max11637 v dd x 0.7 v input hysteresis v hyst 200 mv
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 4 _______________________________________________________________________________________ note 2: limits at t a = -40c are guaranteed by design and not production tested. note 3: tested at v dd = 3v (max11635/max11637); v dd = 5v (max11634/max11636), unipolar input mode. note 4: offset nulled. note 5: time for reference to power up and settle to within 1 lsb. note 6: conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. note 7: the operational input voltage range for each individual input of a differentially configured pair is from gnd to v dd . the operational input voltage difference is from -v ref /2 to +v ref /2. note 8: see figure 3 (equivalent input circuit) and the sampling error vs. source impedance curve in the typical operating characteristics section. note 9: when cnvst is configured as a digital input, do not apply a voltage between v il and v ih . note 10: supply current is specified depending on whether an internal or external reference is used for voltage conversions. temperature measurements always use the internal reference. electrical characteristics (continued) (v dd = 2.7v to 3.6v (max11635/max11637), v dd = 4.75v to 5.25v (max11634/max11636), f sample = 300khz, f sclk = 4.8mhz (external clock, 50% duty cycle), v ref = 2.5v (max11635/max11637), v ref = 4.096v (max11634/max11636) t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units input leakage current i in v in = 0v or v dd 0.01 1.0 a input capacitance c in 15 pf digital outputs (dout, eoc) i sink = 2ma 0.4 output voltage low v ol i sink = 4ma 0.8 v output voltage high v oh i source = 1.5ma v dd - 0.5 v three-state leakage current i l cs = v dd 0.05 1 a three-state output capacitance c out cs = v dd 15 pf power requirements max11634/max11636 4.75 5.25 supply voltage v dd max11635/max11637 2.7 3.6 v f sample = 300ksps 1750 2000 f sample = 0, ref on 1000 1200 internal reference shutdown 0.2 5 f sample = 300ksps 1050 1200 max11635/max11637 supply current (note 10) i dd external reference shutdown 0.2 5 a f sample = 300ksps 2300 2550 f sample = 0, ref on 1050 1350 internal reference shutdown 0.2 5 f sample = 300ksps 1500 1700 max11634/max11636 supply current (note 10) i dd external reference shutdown 0.2 5 a v dd = 2.7v to 3.6v, full-scale input 0.2 1 power-supply rejection psr v dd = 4.75v to 5.25v, full-scale input 0.2 1.4 mv
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference _______________________________________________________________________________________ 5 parameter symbol conditions min typ max units externally clocked conversion 208 sclk clock period t cp data i/o 100 ns sclk pulse-width high t ch 40 ns sclk pulse-width low t cl 40 ns sclk fall to dout transition t dot c load = 30pf 40 ns cs rise to dout disable t dod c load = 30pf 40 ns cs fall to dout enable t doe c load = 30pf 40 ns din to sclk rise setup t ds 40 ns sclk rise to din hold t dh 0 ns cs low to sclk setup t css0 40 ns cs high to sclk setup t css1 40 ns cs high after sclk hold t csh1 0 ns cs low after sclk hold t csh0 0 4 s t cspw cksel = 00 40 ns cnvst pulse-width low cksel = 01 1.4 s voltage conversion 7 cs or cnvst rise to eoc low (note 11) reference power-up 65 s timing characteristics (figure 1) note 11: this time is defined as the number of clock cycles needed for conversion multiplied by the clock period. if the internal reference needs to be powered up, the total time is additive. the internal reference is always used for temperature measurements. typical operating characteristics (v dd = 3v, v ref = 2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11635/max11637, unless otherwise noted. v dd = 5v, v ref = 4.096v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11634/max11636, unless otherwise noted.) integral nonlinearity vs. output code max11634 toc01 output code (decimal) inl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 04096 max11634/max11636 f sample = 300ksps integral nonlinearity vs. output code max11634 toc02 output code (decimal) inl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 04096 max11635/max11637 f sample = 300ksps differential nonlinearity vs. output code max11634 toc03 output code (decimal) dnl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 max11634/max11636 f sample = 300ksps
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 3v, v ref = 2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11635/max11637, unless otherwise noted. v dd = 5v, v ref = 4.096v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11634/max11636, unless otherwise noted.) differential nonlinearity vs. output code max11634 toc04 output code (decimal) dnl (lsb) 3072 2048 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 4096 max11635/max11637 f sample = 300ksps sinad vs. frequency max11634 toc05 frequency (khz) sinad (db) 100 10 55 60 65 70 75 80 50 1 1000 max11635/max11637 max11634/max11636 sfdr vs. frequency max11634 toc06 frequency (khz) sfdr (db) 100 10 60 70 80 90 100 50 11000 max11635/max11637 max11634/max11636 thd vs. frequency max11634 toc07 frequency (khz) thd (db) 100 10 -90 -80 -70 -60 -50 -100 1 1000 max11634/max11636 max11635/max11637 supply current vs. sampling rate max11634 toc08 sampling rate (ksps) i dd (a) 100 10 500 1000 1500 2000 2500 3000 0 11000 max11634/max11636 v dd = 5v internal reference external reference supply current vs. sampling rate max11634 toc09 sampling rate (ksps) i dd (a) 100 10 200 400 600 800 1000 1200 1400 1600 1800 0 1 1000 internal reference external reference max11635/max11637 v dd = 3v supply current vs. supply voltage max11634 toc10 v dd (v) i dd (a) 5.15 4.85 5.05 4.95 1200 1400 1600 1800 2000 2200 2400 2600 1000 4.75 5.25 max11634/max11636 f sample = 300ksps internal reference external reference
max11634?ax11637 12-bit 300ksps adcs with fifo, temp sensor, internal reference _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v dd = 3v, v ref = 2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11635/max11637, unless otherwise noted. v dd = 5v, v ref = 4.096v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11634/max11636, unless otherwise noted.) v dd (v) i dd (a) supply current vs. supply voltage max11634 toc11 3.5 3.6 3.3 3.4 2.9 3.0 3.1 3.2 2.8 200 400 600 800 1000 1200 1400 1600 1800 2000 0 2.7 internal reference external reference max11635/max11637 f sample = 300ksps shutdown supply current vs. supply voltage max11634 toc12 v dd (v) i dd (a) 5.15 4.85 5.05 4.95 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 4.75 5.25 max11634/max11636 v dd = 5v shutdown supply current vs. supply voltage max11634 toc13 v dd (v) i dd (a) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 0.1 0.2 0.3 0.4 0.5 0 2.7 3.6 max11635/max11637 v dd = 3v supply current vs. temperature max11634 toc14 temperature (c) i dd (a) 60 35 10 -15 1300 1600 1900 2200 2500 1000 -40 85 max11634/max11636 v dd = 5v f sample = 300ksps internal reference external reference supply current vs. temperature max11634 toc15 temperature (c) i dd (a) 60 35 10 -15 800 1000 1200 1400 1600 1800 600 -40 85 max11635/max11637 v dd = 3v f sample = 300ksps internal reference external reference shutdown supply current vs. temperature max11634 toc16 temperature (c) i dd (a) 60 35 10 -15 0.5 1.0 1.5 2.0 2.5 0 -40 85 max11634/max11636 v dd = 5v shutdown supply current vs. temperature max11634 toc17 temperature (c) i dd (a) 60 35 10 -15 0.2 0.4 0.6 0.8 1.0 0 -40 85 max11635/max11637 v dd = 3v
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 8 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = 3v, v ref = 2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11635/max11637, unless otherwise noted. v dd = 5v, v ref = 4.096v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11634/max11636, unless otherwise noted.) internal reference voltage vs. supply voltage max11634 toc18 v dd (v) v ref (v) 5.15 5.05 4.95 4.85 4.095 4.096 4.097 4.098 4.099 4.094 4.75 5.25 max11634/max11636 v dd = 5v internal reference voltage vs. supply voltage max11634 toc19 v dd (v) v ref (v) 3.3 3.0 2.498 2.499 2.500 2.501 2.502 2.497 2.7 3.6 max11635/max11637 v dd = 3v internal reference voltage vs. temperature max11634 toc20 temperature (c) v ref (v) 60 35 10 -15 4.08 4.09 4.10 4.11 4.12 4.07 -40 85 max11634/max11636 v dd = 5v internal reference voltage vs. temperature max11634 toc21 temperature (c) v ref (v) 60 35 10 -15 2.48 2.49 2.50 2.51 2.52 2.47 -40 85 max11635/max11637 v dd = 3v offset error vs. supply voltage max11634 toc22 v dd (v) offset error (lsb) 5.15 5.05 4.95 4.85 -0.4 -0.2 0 0.2 0.4 0.6 -0.6 4.75 5.25 max11634/max11636 f sample = 300ksps offset error vs. supply voltage max11634 toc23 v dd (v) offset error (lsb) 3.3 3.0 0.95 1.00 1.05 1.10 0.90 2.7 3.6 max11635/max11637 f sample = 300ksps offset error vs. temperature max11634 toc24 temperature (c) offset error (lsb) 60 35 10 -15 -0.6 -0.2 0.2 0.6 1.0 -1.0 -40 85 max11634/max11636 f sample = 300ksps
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference _______________________________________________________________________________________ 9 typical operating characteristics (continued) (v dd = 3v, v ref = 2.5v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11635/max11637, unless otherwise noted. v dd = 5v, v ref = 4.096v, f sclk = 4.8mhz, c load = 30pf, t a = +25c for max11634/max11636, unless otherwise noted.) offset error vs. temperature max11634 toc25 temperature (c) offset error (lsb) 60 35 10 -15 0.7 0.9 1.1 1.3 1.5 0.5 -40 85 max11635/max11637 f sample = 300ksps gain error vs. supply voltage max11634 toc26 v dd (v) gain error (lsb) 5.15 5.05 4.95 4.85 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 4.75 5.25 max11634/max11636 f sample = 300ksps gain error vs. supply voltage max11634 toc27 v dd (v) gain error (lsb) 3.3 3.0 -0.4 -0.3 -0.2 -0.1 0 -0.5 2.7 3.6 max11635/max11637 f sample = 300ksps gain error vs. temperature max11634 toc28 temperature (c) gain error (lsb) 60 35 10 -15 -0.6 -0.2 0.2 0.6 1.0 -1.0 -40 85 max11634/max11636 f sample = 300ksps gain error vs. temperature max11634 toc29 temperature (c) gain error (lsb) 60 35 10 -15 -0.3 -0.1 0.1 0.3 0.5 -0.5 -40 85 max11635/max11637 f sample = 300ksps -10 -6 -8 -2 -4 0 2 04 26810 sampling error vs. source impedance max11634 toc30 source impedance (k ? ) sampling error (lsb)
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 10 ______________________________________________________________________________________ pin description pin max11634 max11635 max11636 max11637 name function 1C4 ain0Cain3 analog inputs 5, 6 n.c. no connection. not internally connected. 7 ref- external differential reference negative input 8 cnvst active-low conversion start input. see table 3 for details on programming the setup register. 9 9 ref+ positive reference input. bypass to gnd with a 0.1f capacitor. 10 10 gnd ground 11 11 v dd power input. bypass to gnd with a 0.1f capacitor. 12 12 cs active-low chip-select input. when cs is high, dout is high impedance. 13 13 sclk serial-clock input. clocks data in and out of the serial interface (duty cycle must be 40% to 60%). see table 3 for details on programming the clock mode. 14 14 din serial-data input. din data is latched into the serial interface on the rising edge of sclk. 15 15 dout serial-data output. data is clocked out on the falling edge of sclk. high impedance when cs is connected to v dd . 16 16 eoc active-low end-of-conversion output. data is valid after eoc pulls low. 1C6 ain0Cain5 analog inputs 7 ref-/ain6 external differential reference negative input/analog input 6. see table 3 for details on programming the setup register. 8 cnvst /ain7 active-low conversion start input/analog input 7. see table 3 for details on programming the setup register. 16 15 14 13 12 11 10 9 2 1 3 4 5 6 7 8 ain0 ( ) pinout for the max11634/max11635. top view eoc dout din sclk cs v dd gnd ref+ max11634 max11637 qsop ain1 ain2 ain5 (n.c.) ain3 ain4 (n.c.) ref-/ain6 (ref-) cnvst/ain7 (cnvst) + pin configuration
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference ______________________________________________________________________________________ 11 detailed description the max11634Cmax11637 are low-power, serial-out- put, multichannel adcs for temperature-control, process-control, and monitoring applications. these 12-bit adcs have internal track and hold (t/h) circuitry that supports single-ended and fully differential inputs. data is converted from analog voltage sources in a variety of chan nel and data-acquisition configurations. microprocessor (p) control is made easy through a 3- wire spi/qspi/microwire-compatible serial interface. figure 2 shows a simplified functional diagram of the max11634Cmax11637 internal architecture. the max11636/max11637 have eight single-ended analog input channels or four differential channels. the max11634/max11635 have four single-ended analog input channels or two differential channels. sclk din dout cs t dh t doe t ds t ch t cl t css0 t cp t csh1 t csh0 t css1 t dod t dot figure 1. detailed serial-interface timing diagram 12-bit sar adc control serial interface oscillator fifo and accumulator t/h ref- cnvst sclk cs din eoc dout ain7 ain0 ain1 internal reference ref+ max11634?ax11637 figure 2. functional diagram
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 12 ______________________________________________________________________________________ converter operation the max11634Cmax11637 adcs use a fully differen- tial, successive-approximation register (sar) conver- sion technique and an on-chip t/h block to convert temperature and voltage signals into a 12-bit digital result. both single-ended and differential configurations are supported, with a unipolar signal range for single- ended mode and bipolar or unipolar ranges for differ- ential mode. input bandwidth the adcs input-tracking circuitry has a 1mhz small- signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the adcs sampling rate by using undersampling techniques. anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. analog input protection internal esd protection diodes clamp all pins to v dd and gnd, allowing the inputs to swing from (gnd - 0.3v) to (v dd + 0.3v) without damage. however, for accurate conversions near full scale, the inputs must not exceed v dd by more than 50mv or be lower than gnd by 50mv. if an off-channel analog input voltage exceeds the supplies, limit the input current to 2ma. 3-wire serial interface the max11634Cmax11637 feature a serial interface compatible with spi/qspi and microwire devices. for spi/qspi, ensure the cpu serial interface runs in master mode so it generates the serial clock signal. select the sclk frequency of 10mhz or less, and set clock polarity (cpol) and phase (cpha) in the p con- trol registers to the same value. the max11634C max11637 operate with sclk idling high or low, and thus operate with cpol = cpha = 0 or cpol = cpha = 1. set cs low to latch input data at din on the rising edge of sclk. output data at dout is updated on the falling edge of sclk. bipolar true differential results are available in twos complement format, while all others are in binary. serial communication always begins with an 8-bit input data byte (msb first) loaded from din. use a second byte, immediately following the setup byte, to write to the unipolar mode or bipolar mode registers (see tables 1, 3, 4, and 5). a high-to-low transition on cs ini- tiates the data input operation. the input data byte and the subsequent data bytes are clocked from din into the serial interface on the rising edge of sclk. tables 1C7 detail the register descriptions. bits 5 and 4, cksel1 and cksel0, respectively, control the clock modes in the setup register (see table 3). choose between four different clock modes for various ways to start a conversion and determine whether the acquisi- tions are internally or externally timed. select clock mode 00 to configure cnvst /ain7 to act as a conver- sion start and use it to request the programmed, inter- nally timed conversions without tying up the serial bus. in clock mode 01, use cnvst to request conversions one channel at a time, controlling the sampling speed without tying up the serial bus. request and start inter- nally timed conversions through the serial interface by writing to the conversion register in the default clock mode 10. use clock mode 11 with sclk up to 4.8mhz for externally timed acquisitions to achieve sampling rates up to 300ksps. clock mode 11 disables scanning and averaging. see figures 4C7 for timing specifica- tions and how to begin a conversion. these devices feature an active-low, end-of-conversion output. eoc goes low when the adc completes the last- requested operation and is waiting for the next input data byte (for clock modes 00 and 10). in clock mode 01, eoc goes low after the adc completes each requested operation. eoc goes high when cs or cnvst goes low. eoc is always high in clock mode 11. single-ended/differential input the max11634Cmax11637 use a fully differential adc for all conversions. the analog inputs can be config- ured for either differential or single-ended conversions by writing to the setup register (see table 3). single- ended conversions are internally referenced to gnd (see figure 3). in differential mode, the t/h samples the difference between two analog inputs, eliminating common-mode dc offsets and noise. in+ and in- are selected from the following pairs: ain0/ain1, ain2/ain3, ain4/ain5, and ain6/ain7. ain0Cain7 are available on the max11636/ max11637. ain0Cain3 are available on the max11634/ max11635. see tables 2C5 for more details on config- uring the inputs. for the inputs that can be configured as cnvst or an analog input, only one can be used at a time. for the inputs that can be configured as ref- or an analog input, the ref- configuration excludes the analog input.
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference ______________________________________________________________________________________ 13 unipolar/bipolar address the unipolar and bipolar registers through the setup register (bits 1 and 0). program a pair of analog channels for differential operation by writing a 1 to the appropriate bit of the bipolar or unipolar register. unipolar mode sets the differential input range from 0 to v ref . a negative differential analog input in unipolar mode causes the digital output code to be zero. selecting bipolar mode sets the differential input range to v ref /2. the digital output code is binary in unipolar mode and twos complement in bipolar mode (figures 8 and 9). in single-ended mode, the max11634Cmax11637 always operate in unipolar mode. the analog inputs are internally referenced to gnd with a full-scale input range from 0 to v ref . true differential analog input t/h the equivalent circuit of figure 3 shows the max11634Cmax11637s input architecture. in track mode, a positive input capacitor is connected to ain0Cain7 in single-ended mode (and ain0, ain2, ain4, ain5, ain6 in differential mode). a negative input capacitor is connected to gnd in single-ended mode (or ain1, ain3, ain5, ain6, ain7 in differential mode). for external t/h timing, use clock mode 01. after the t/h enters hold mode, the difference between the sam- pled positive and negative input voltages is converted. the time required for the t/h to acquire an input signal is determined by how quickly its input capacitance is charged. if the input signals source impedance is high, the required acquisition time lengthens. the acquisition time, t acq , is the maximum time needed for a signal to be acquired, plus the power-up time. it is calculated by the following equation: t acq = 9 x (r s + r in ) x 24pf + t pwr where r in = 1.5k ? , r s is the source impedance of the input signal, and t pwr = 1s, the power-up time of the device. the varying power-up times are detailed in the explanation of the clock mode conversions. when the conversion is internally timed, t acq is never less than 1.4s, and any source impedance below 300 ? does not significantly affect the adcs ac perfor- mance. a high-impedance source can be accommo- dated either by lengthening t acq or by placing a 1f capacitor between the positive and negative analog inputs. internal fifo the max11634Cmax11637 contain a fifo buffer that can hold up to 16 adc results. this allows the adc to handle multiple internally clocked conversions without tying up the serial bus. if the fifo is filled and further conversions are requested without reading from the fifo, the oldest adc results are overwritten by the new adc results. each result contains 2 bytes, with the msb preceded by four lead- ing zeros. after each falling edge of cs , the oldest available byte of data is available at dout, msb first. when the fifo is empty, dout is zero. internal clock the max11634Cmax11637 operate from an internal oscillator, which is accurate within 10% of the 4.4mhz nominal clock rate. the internal oscillator is active in clock modes 00, 01, and 10. read out the data at clock speeds up to 10mhz. see figures 4C7 for details on timing specifications and starting a conversion. + - hold cin+ ref gnd dac cin- v dd /2 comparator ain0?in7 (single-ended); ain0, ain2, ain4, ain6 (differential) gnd (single-ended); ain1, ain3, ain5, ain7 (differential) hold hold figure 3. equivalent input circuit
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 14 ______________________________________________________________________________________ applications information register descriptions the max11634Cmax11637 communicate between the internal registers and the external circuitry through the spi/qspi-compatible serial interface. table 1 details the registers and the bit names. tables 2C7 show the various functions within the conversion register, setup register, averaging register, reset register, unipolar reg- ister, and bipolar register. conversion time calculations the conversion time for each scan is based on a num- ber of different factors: conversion time per sample, samples per result, results per scan, and if the external reference is in use. use the following formula to calculate the total conver- sion time for an internally timed conversion in clock modes 00 and 10 (see the electrical characteristics table as applicable): total conversion time = t cnv x n avg x n result + t rp where: t cnv = t acq (max) + t conv (max) n avg = samples per result (amount of averaging) n result = number of fifo results requested; deter- mined by number of channels being scanned or by nscan1, nscan0 t rp = internal reference wake up; set to zero if internal reference is already powered up or external reference is being used in clock mode 01, the total conversion time depends on how long cnvst is held low or high, including any time required to turn on the internal reference. conversion time in externally clocked mode (cksel1, cksel0 = 11) depends on the sclk period and how long cs is held high between each set of eight sclk cycles. in clock mode 01, the total conversion time does not include the time required to turn on the internal reference. conversion register select active analog input channels and scan modes by writing to the conversion register. table 2 details channel selection, the four scan modes, and how to request a temperature measurement. request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the cnvst pin when in clock mode 00 or 01. a conversion is not performed if it is requested on a channel that has been configured as cnvst or ref-. do not request conversions on channels 4C7 on the max11634/max11635. set chsel[2:0] to the lower channels binary values. if the last two channels are configured as a differential pair and one of them has been reconfigured as cnvst or ref-, the pair is ignored. select scan mode 00 or 01 to return one result per single-ended channel and one result per differential pair within the requested range. select scan mode 10 to scan a single input channel numerous times, depending on nscan1 and nscan0 in the averag- ing register (table 6). select scan mode 11 to return only one result from a single channel. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 conversion 1 x chsel2 chsel1 chsel0 scan1 scan0 x setup 0 1 cksel1 cksel0 refsel1 refsel0 diffsel1 diffsel0 averaging 0 0 1 avgon navg1 navg0 nscan1 nscan0 reset 0 0 0 1 reset x x x unipolar mode (setup) uch0/1 uch2/3 uch4/5 uch6/7 x x x x bipolar mode (setup) bch0/1 bch1/2 bch4/5 bch6/7 x x x x table 1. input data byte (msb first) x = dont care.
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference ______________________________________________________________________________________ 15 setup register write a byte to the setup register to configure the clock, reference, and power-down modes. table 3 details the bits in the setup register. bits 5 and 4 (cksel1 and cksel0) control the clock mode, acquisition and sam- pling, and the conversion start. bits 3 and 2 (refsel1 and refsel0) control internal or external reference use. bits 1 and 0 (diffsel1 and diffsel0) address the unipolar mode and bipolar mode registers and configure the analog input channels for differential operation. unipolar/bipolar mode registers the final 2 bits (lsbs) of the setup register control the unipolar/bipolar mode address registers. set bits 1 and 0 (diffsel1 and diffsel0) to 10 to write to the unipo- lar mode register. set bits 1 and 0 to 11 to write to the bipolar mode register. in both cases, the setup byte must be followed immediately by 1 byte of data written to the unipolar register or bipolar register. hold cs low and run 16 sclk cycles before pulling cs high. if the last 2 bits of the setup register are 00 or 01, neither the unipolar mode register nor the bipolar mode register is written. any subsequent byte is recognized as a new input data byte. see tables 4 and 5 to program the unipolar and bipolar mode registers. if a channel is configured as both unipolar and bipolar, the unipolar setting takes precedence. in unipolar mode, ain+ can exceed ain- by up to v ref . the out- put format in unipolar mode is binary. in bipolar mode, either input can exceed the other by up to v ref /2. the output format in bipolar mode is two's complement. averaging register write to the averaging register to configure the adc to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans. table 2 details the four scan modes available in the con- version register. all four scan modes allow averaging as long as the avgon bit, bit 4 in the averaging register, is set to 1. select scan mode 10 to scan the same channel multiple times. clock mode 11 disables averaging. reset register write to the reset register (as shown in table 7) to clear the fifo or to reset all registers to their default states. set the reset bit to 1 to reset the fifo. set the reset bit to zero to return the max11634Cmax11637 to the default power-up state. power-up default state the max11634Cmax11637 power up with all blocks in shutdown, including the reference. all registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (cksel1 = 1). bit name bit function 7 (msb) set to 1 to select conversion register x 6 dont care chsel2 5 analog input channel select chsel1 4 analog input channel select chsel0 3 analog input channel select scan1 2 scan mode select scan0 1 scan mode select x 0 (lsb) dont care table 2. conversion register* * see below for bit details. chsel2 chsel1 chsel0 selected channel (n) 0 0 0 ain0 0 0 1 ain1 0 1 0 ain2 0 1 1 ain3 1 0 0 ain4 1 0 1 ain5 1 1 0 ain6 1 1 1 ain7 scan1 scan0 scan mode (channel n is selected by bits chsel[2:0]) 0 0 scans channels 0 through n 0 1 scans channels n through the highest numbered channel 1 0 scans channel n repeatedly. the averaging register sets the number of results. 1 1 no scan. converts channel n once only.
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 16 ______________________________________________________________________________________ table 3. setup register* bit name bit function 7 (msb) set to 0 to select setup register 6 set to 1 to select setup register cksel1 5 clock mode and cnvst configuration. resets to 1 at power-up. cksel0 4 clock mode and cnvst configuration refsel1 3 reference mode configuration refsel0 2 reference mode configuration diffsel1 1 unipolar/bipolar mode register configuration for differential mode diffsel0 0 (lsb) unipolar/bipolar mode register configuration for differential mode cksel1 cksel0 conversion clock acquisition/sampling cnvst configuration 0 0 internal internally timed cnvst 0 1 internal externally timed through cnvst cnvst 1 0 internal internally timed ain7* 1 1 external (4.8mhz max) externally timed through sclk ain7* refsel1 refsel0 voltage reference autoshutdown ref- configuration 0 0 internal reference off after scan; need wake-up delay ain6 0 1 external single-ended reference off; no wake-up delay ain6 1 0 internal reference always on; no wake- up delay ain6 1 1 external differential reference off; no wake-up delay ref-* diffsel1 diffsel0 function 0 0 no data follows the setup byte. unipolar mode and bipolar mode registers remain unchanged. 0 1 no data follows the setup byte. unipolar mode and bipolar mode registers remain unchanged. 1 0 1 byte of data follows the setup byte and is written to the unipolar mode register. 1 1 1 byte of data follows the setup byte and is written to the bipolar mode register. * see below for bit details. * the max11634/max11635 have a dedicated cnvst pin. * the max11634/max11635 have a dedicated ref- pin.
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference ______________________________________________________________________________________ 17 output data format figures 4C7 illustrate the conversion timing for the max11634Cmax11637. the 12-bit conversion result is output in msb-first format with four leading zeros. din data is latched into the serial interface on the rising edge of sclk. data on dout transitions on the falling edge of sclk. conversions in clock modes 00 and 01 are initiated by cnvst . conversions in clock modes 10 and 11 are initiated by writing an input data byte to the conversion register. data is binary for unipolar mode and twos complement for bipolar mode. bit name bit function uch0/1 7 (msb) set to 1 to configure ain0 and ain1 for unipolar differential conversion uch2/3 6 set to 1 to configure ain2 and ain3 for unipolar differential conversion uch4/5 5 set to 1 to configure ain4 and ain5 for unipolar differential conversion uch6/7 4 set to 1 to configure ain6 and ain7 for unipolar differential conversion x 3 dont care x 2 dont care x 1 dont care x 0 (lsb) dont care table 4. unipolar mode register (addressed through setup register) bit name bit function bch0/1 7 (msb) set to 1 to configure ain0 and ain1 for bipolar differential conversion bch2/3 6 set to 1 to configure ain2 and ain3 for bipolar differential conversion bch4/5 5 set to 1 to configure ain4 and ain5 for bipolar differential conversion bch6/7 4 set to 1 to configure ain6 and ain7 for bipolar differential conversion x 3 dont care x 2 dont care x 1 dont care x 0 (lsb) dont care table 5. bipolar mode register (addressed through setup register)
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 18 ______________________________________________________________________________________ bit name bit function 7 (msb) set to 0 to select averaging register 6 set to 0 to select averaging register 5 set to 1 to select averaging register avgon 4 set to 1 to turn averaging on. set to 0 to turn averaging off. navg1 3 configures the number of conversions for single-channel scans navg0 2 configures the number of conversions for single-channel scans nscan1 1 single-channel scan count (scan mode 10 only) nscan0 0 (lsb) single-channel scan count (scan mode 10 only) table 6. averaging register* avgon navg1 navg0 function 0 x x performs 1 conversion for each requested result 1 0 0 performs 4 conversions and returns the average for each requested result 1 0 1 performs 8 conversions and returns the average for each requested result 1 1 0 performs 16 conversions and returns the average for each requested result 1 1 1 performs 32 conversions and returns the average for each requested result nscan1 nscan0 function (applies only if scan mode 10 is selected) 0 0 scans channel n and returns 4 results 0 1 scans channel n and returns 8 results 1 0 scans channel n and returns 12 results 1 1 scans channel n and returns 16 results bit name bit function 7 (msb) set to 0 to select reset register 6 set to 0 to select reset register 5 set to 0 to select reset register 4 set to 1 to select reset register reset 3 set to 0 to reset all registers; set to 1 to clear the fifo only x 2 dont care x 1 dont care x 0 (lsb) dont care table 7. reset register * see below for bit details.
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference ______________________________________________________________________________________ 19 internally timed acquisitions and conversions using cnvst performing conversions in clock mode 00 in clock mode 00, the wake-up, acquisition, conversion, and shutdown sequences are initiated through cnvst and performed automatically using the internal oscilla- tor. results are added to the internal fifo to be read out later. see figure 4 for clock mode 00 timing. initiate a scan by setting cnvst low for at least 40ns before pulling it high again. the max11634Cmax11637 then wake up, scan all requested channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are avail- able in the fifo. wait until eoc goes low before pulling cs low to communicate with the serial interface. eoc stays low until cs or cnvst is pulled low again. do not initiate a second cnvst before eoc goes low; otherwise, the fifo can become corrupted. externally timed acquisitions and internally timed conversions with cnvst performing conversions in clock mode 01 in clock mode 01, conversions are requested one at a time using cnvst and performed automatically using the internal oscillator. see figure 5 for clock mode 01 timing. setting cnvst low begins an acquisition, wakes up the adc, and places it in track mode. hold cnvst low for at least 1.4s to complete the acquisition. if the internal reference needs to wake up, an additional 65s is required for the internal reference to power up. if a tem- perature measurement is being requested, reference power-up and temperature measurement are internally timed. in this case, hold cnvst low for at least 40ns. set cnvst high to begin a conversion. after the con- version is complete, the adc shuts down and pulls eoc low. eoc stays low until cs or cnvst is pulled low again. wait until eoc goes low before pulling cs or cnvst low. if averaging is turned on, multiple cnvst pulses need to be performed before a result is written to the fifo. once the proper number of conversions has been per- formed to generate an averaged fifo result, as speci- fied by the averaging register, the scan logic automatically switches the analog input multiplexer to the next requested channel. the result is available on dout once eoc has been pulled low. (up to 514 internally clocked acquisitions and conversions) cs dout msb1 lsb1 msb2 sclk cnvst eoc set cnvst low for at least 40ns to begin a conversion. figure 4. clock mode 00
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference 20 ______________________________________________________________________________________ internally timed acquisitions and conversions using the serial interface performing conversions in clock mode 10 in clock mode 10, the wake-up, acquisition, conversion, and shutdown sequences are initiated by writing an input data byte to the conversion register, and are per- formed automatically using the internal oscillator. this is the default clock mode upon power-up. see figure 6 for clock mode 10 timing. initiate a scan by writing a byte to the conversion regis- ter. the max11634Cmax11637 then power up, scan all requested channels, store the results in the fifo, and shut down. after the scan is complete, eoc is pulled low and the results are available in the fifo. eoc stays low until cs is pulled low again. externally clocked acquisitions and conversions using the serial interface performing conversions in clock mode 11 in clock mode 11, acquisitions and conversions are ini- tiated by writing to the conversion register and are per- formed one at a time using the sclk as the conversion clock. scanning and averaging are disabled, and the conversion result is available at dout during the con- version. see figure 7 for clock mode 11 timing. initiate a conversion by writing a byte to the conversion register followed by 16 sclk cycles. if cs is pulsed high between the eighth and ninth cycles, the pulse width must be less than 100s. to continuously convert at 16 cycles per conversion, alternate 1 byte of zeros between each conversion byte. cs dout sclk cnvst eoc (conversion2) msb1 lsb1 msb2 (acquisition1) (acquisition2) (conversion1) request multiple conversions by setting cnvst low for each conversion. figure 5. clock mode 01 (up to 514 internall clocked acquisitions and conversions) msb1 lsb1 msb2 (conversion bte) cs dout sclk din eoc the conversion bte begins the acquisition. cnvst is not required. figure 6. clock mode 10
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference ______________________________________________________________________________________ 21 partial reads and partial writes if the first byte of an entry in the fifo is partially read ( cs is pulled high after fewer than eight sclk cycles), the second byte of data that is read out contains the next 8 bits (not b[7:0]). the remaining bits are lost for that entry. if the first byte of an entry in the fifo is read out fully, but the second byte is read out partially, the rest of the entry is lost. the remaining data in the fifo is uncorrupted and can be read out normally after tak- ing cs low again, as long as the four leading bits (nor- mally zeros) are ignored. internal registers that are written partially through the spi contain new values, starting at the msb up to the point that the partial write is stopped. the part of the register that is not written contains previously written values. if cs is pulled low before eoc goes low, a conversion cannot be complet- ed and the fifo is corrupted. transfer function figure 8 shows the unipolar transfer function for single- ended or differential inputs. figure 9 shows the bipolar transfer function for differential inputs. code transitions occur halfway between successive-integer lsb values. output coding is binary, with 1 lsb = v ref /4096 for unipolar and bipolar operation, and 1 lsb = 0.125? for temperature measurements. layout, grounding, and bypassing for best performance, use pc boards. do not use wire- wrap boards. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digital (especially clock) signals parallel to one another or run digital lines underneath the max11634?ax11637 package. high-frequency noise in the v dd power supply can affect performance. bypass the v dd supply with a 0.1? capacitor to gnd, close to the v dd pin. minimize capacitor lead lengths for best supply-noise rejection. if the power supply is very noisy, connect a 10 ? resistor in series with the supply to improve power-supply filtering. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. inl for the max11634?ax11637 is measured using the end- point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. cs dout sclk din eoc msb1 lsb1 msb2 (acquisition1) (acquisition2) (conversion1) (conversion byte) externally timed acquisition, sampling and conversion without cnvst. figure 7. clock mode 11
max11634?ax11637 signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization error only and results directly from the adcs resolution (n bits): snr = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise, including thermal noise, reference noise, clock jitter, etc. therefore, snr is calculated by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamen- tal, the first five harmonics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequencys rms amplitude to the rms equivalent of all other adc output signals: sinad (db) = 20 x log (signal rms /noise rms ) effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc error consists of quantiza- tion noise only. with an input range equal to the full- scale range of the adc, calculate the effective number of bits as follows: enob = (sinad - 1.76)/6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 Cv 5 are the amplitudes of the 2nd-order to 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest distor- tion component. log thd x vvvv v = +++ () ? ? 20 2 2 3 2 4 2 5 2 1 ? ? ? ? ? 12-bit, 300ksps adcs with differential track/hold, and internal reference 22 ______________________________________________________________________________________ figure 9. bipolar transfer function, full scale (fs) = v ref /2 output code full-scale transition 11. . .111 11. . .110 11. . .101 00. . .011 00. . .010 00. . . 001 00. . . 000 123 0 (com) fs fs - 3/2 lsb fs = v ref + v com zs = v com input voltage (lsb) 1 lsb = v ref 4096 011. . . 111 011. . .110 000. . . 010 000. . .001 000. . .000 111 . . .111 111 . . . 110 111 . . . 101 100 . . . 001 100. . . 000 - fs com* input voltage (lsb) output code zs = com +fs - 1 lsb *v com v ref / 2 + v com + v com fs = v ref 2 -fs = -v ref 2 1 lsb = v ref 4096 figure 8. unipolar transfer function, full scale (fs) = v ref
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference ______________________________________________________________________________________ 23 chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 qsop e16+5 21-0055 90-0167
max11634?ax11637 12-bit, 300ksps adcs with differential track/hold, and internal reference maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/11 initial release 1 9/11 released the max11636/max11637 and revised the transfer function section. 1, 21

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